Designing a Multiprocessor Cache subsystem: Everything you need to know about Multiprocessing, load store sections, L1/L2 caches, MMU’s, BIU’s, prefetchers and mem-copy optimizations

his book has been written by an industry veteran with 25 years of experience working for companies like AMD, Intel, ADI, TI and Samsung designing microprocessors (cache subsystems specifically) for computers, tablets and smartphones.  The author has a Master's degree in Computer Engineering from The University of Texas at Austin. This book provides an in-depth review of designing multiprocessor cache subsystems which encompasses the entire memory hierarchy inside a multiprocessor cluster. The memory hierarchy includes load store section, L1  cache, L1 MMU, L2 MMU/Walk unit , Prefetcher inside a processor.  The multiprocessor cluster has multiple such processors which talk to a shared L2 and BIU. Three level hierarchies are covered as well. Topics like coherency, consistency, memory instruction set, multiprocessing basics and advanced multiprocessing topics, livelocks, deadlocks, starvation, microarchitecture of the memory hierarchy components (like Load store section, L2 caches etc) mentioned above, memory copy measurements and optimizations, bus interfaces are covered in great detail. This book is intended for students pursuing engineering degrees in Computer engineering, Electrical engineering, Computer Science, designers and verification engineers working on processor designs and anyone interested in knowing more about multiprocessor cache subsystems. Read more